Design & Implementation of Low Power Full Adder Cell Using Power Gating Techniques for Mobile Applications
For the foremost recent CMOS feature sizes (e.g., 180nm), run power dissipation has become associate in nursing paramount concern for VLSI circuit designers. As technology scales into the nano-meter regime run power and noise immunity are getting vital metric of comparable importance to active power, delay and space for the analysis and style of complicated arithmetic and logic circuits. During this paper, low run 1-bit full adder cells square measure projected for mobile applications. Noise immunity has been rigorously thought-about since the numerous threshold current of the low threshold voltage transition becomes additional vulnerable to noise.