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Parallel prefix adder is a technique for increasing the speed in DSP processor while performing addition process. The proposed 64-bit adder is designed using four different types prefix cell operators in transmission gate technique. The power and area comparison can be made with CMOS implementation of various types parallel prefix adder in different input word length. The proposed parallel prefix transmission gate adder consumes less power and less area compared to CMOS style parallel prefix adders. Tanner EDA tool was used for simulating the parallel prefix adder designs in the 250nm technologies.
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