Processors

Design of a Control Logic in a Dynamic Reconfigurable System

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Executive Summary

this paper, the authors propose an architecture for controlling Dynamic Reconfigurable systems. The processor instructions when compiled one by one produces very high delay overhead. If these instructions are converted into a combinational logic then the overhead can be reduced thereby making the system an efficient one. This paper presents a method for creating the control logic necessary for performing operations on instructions. The proposed design is simulated using Modelsim 10.0c.The area and power constraints are evaluated using Synopsys Design Compiler.

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