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In this project a design of high throughput crypto devices based on AES algorithm has been presented. The bus width of the architecture is 128 bit. For the 128 bit input 128 bit key is used. The plain text and the key are used as a inputs. Sub Bytes method has been implemented using both composite field method and fixed Rom for further analysis and comparison of performance. By using S-box and key expansion the throughput has been achieved in the range of Gbps. To obtain a high speed pipelining method has been used in this design. The pipelined architecture of the AES algorithm is proposed in order to increase the throughput of the algorithm.
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