Design of a Quasi-Cyclic LDPC Decoder Using Generic Data Packing Scheme
This paper proposed a generic data packing scheme for quasi-cyclic LDPC codes decoder which has two advantages. Firstly, in this scheme no shift network is needed, it greatly reduces the area of the LDPC decoder. Secondly, in this scheme, all the messages in a row can be accessed from memories in one cycle, it increase the throughput of LDPC decoder. A LDPC decoder architecture using the data packing scheme is proposed. Based on this architecture, a multi rate decoder that supports all code rates and all code lengths in IEEE 802.16e standard is implemented using a SMIC 0.18m CMOS technology.