Design of Adaptive Network-on-Chip Using VLSI Technology
In this paper, the authors propose a memory-efficient on-chip network architecture based router design. In addition to the resource utilization of router design, the high requirements of memories in router architecture design increases the network latency. The area overhead is also reduced by resource multiplexing due to the on-demand buffer assignment at each output port. The proposed work results average network latency(16%) and average memory utilization (22%). The proposed Network-on-Chip (NoC) can be modeled using Verilog HDL and simulated using Modelsim software.