Design of High Efficiency Two Stage Power Amplifier in 0.13UM RF CMOS Technology for 2.4GHZ WLAN Application

A two stage CMOS power amplifier is implemented in 0.13um RF CMOS technology using ADS tool operating at 2.4 GHz with dc supply of 2.5 V. Driver stage as the input stage and power stage as the output stage are the two stages. A cascode topology is used in the driver stage and basic topology is used in the power stage. Output power at 1dB compression point is 20.028 dBm and maximum output power delivered by this circuit is 22.002 dBm. Power added efficiency calculated at 1 dB compression point is 44.669 % whereas the maximum power added efficiency comes out to be 70.196 %.

Provided by: Academy & Industry Research Collaboration Center Topic: Mobility Date Added: Aug 2013 Format: PDF

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