Hardware

Design of High Speed Six Transistor Full Adder Using a Novel Two Transistor XOR Gates

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Executive Summary

In modern era, the numbers of transistors are reduced in the circuit and ultra low power design have emerged as an active research topic due to its various applications. A full adder is one of the essential component in digital circuit design, many improvements have been made to reduce the architecture of a full adder. The main aim of this paper is to reduce the power dissipation and area by redusing the number of transistors. By using general logic of pmos transistor, the two transistor xor gate can be implemented. In this paper proposes the novel design of a 2T XOR gate.

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