Design of Low Power and Fast locking Digital Phase Locked Loop
A Phase Locked Loop (PLL) is a circuit that synchronizes an oscillator's output signal with a reference or input signal in both frequency and phase. The phase error between the oscillator's output signal and the reference signal is constant (not necessarily zero) when the PLL is locked (reference input and oscillator output are synchronized). This paper presents low power and low locking time digital phase locked loop. DPLL is designed and simulated in tanner EDA and by using 0.18um technology. This design is based on current starved voltage controlled oscillator. This design consumes 4.47mW power and takes 0.312us to lock.