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Design of area- and power efficient high-speed data path logic system forms the largest areas of research in VLSI system design. In digital adders, the speed of addition is limited by the time required to transmit a carry through the adder. Carry SeLect Adder (CSLA) is one of the fastest adders used in many data processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is span for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to drastically reduce the area and power of the CSLA.
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