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Low complexity and reconfigurability are reported to be the key features in a Software Defined Radio (SDR). To obtain these features, a reconfigurable architecture based on Frequency Response Masking (FRM) technique can be used for the implementation of the channel filters in the SDR. The frequency response masking approach is proved to be a good candidate for the realization of a sharp digital Finite Impulse Response (FIR) filter with low complexity. To reduce the complexity and power consumption for hardware realization, a design method which makes the channel filters totally multiplier less is proposed in this paper. Continuous filter coefficients are first converted to finite precision coefficients using Signed Power of Two (SPT) space to obtain a multiplier-less filter.
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