Design of Systolic FIR Filter Using VHDL Language
Digital Signal Processing (DSP) is widely used in real-time applications such as video, image processing and wireless communication. Low power consumption and smaller area are the most important criteria in VLSI design. This paper presents an efficient design of FIR filter using systolic structure with the consideration of adders and multipliers as processing elements. In this paper, 4, 8, 16, 32 and 64 tap systolic band pass FIR filter with ultra wide band frequency (3.1GHz to 10.6GHz) is designed and simulated using Xilinx tool Integrated Software Environment (ISE) 13.1.