Design Tradeoffs for Simplicity and Efficient Verification in the Execution Migration Machine
During the past decade, continued growth in transistor densities has permitted increasingly large and complex silicon designs. As transistor technology continues to scale, the architecture community has experienced exponential growth in design complexity and significantly increasing implementation and verification costs. Moreover, Moore's law has led to a ubiquitous trend of an increasing number of cores on a single chip. Often, these large-core-count chips provide a shared memory abstraction via directories and coherence protocols, which have become notoriously error-prone and difficult to verify because of subtle data races and state space explosion.