Designing and Optimizing the Fetch Unit for a RISC Core
Despite the extensive deployment of multi-core architectures in the past few years, the design and optimization of each single processing core is still a fresh field in computing. On the other hand, having a design procedure (used to solve the problems related to the design of a single processing core) makes it possible to apply the proposed solutions to specific-purpose processing cores. The instruction fetch, which is one of the parts of the architectural design, is considered to have the greatest effect on the performance. RISC processors, which have architecture with a high capability for parallelism, need a high instruction width in order to reach an appropriate performance.