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This is designed to the core of a UART interface module, which includes both receive and transmit modules, and the command parser. This paper will be a viable solution to design parallel buses with the help of UART. In the test bench, there is a RFM (Register File Model) to which the authors write/read back data from just to check their design. The txt file issues serial inputs to the core and the core outputs parallel data and address in the form of bus. This bus is connected to their RFM (register file model) instantiated in the test bench along with the design. This makes easy to retrieve parallel data from serial input.
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