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With the advent of diversifie network services and programmability deployed in the network infrastructure, the functionality of the data path in network systems has moved from "Store-And-Forward" toward "Store-Process-Forward." However, the processing performance of many contemporary software routers does not scale with the increasing number of processor cores that are integrated on a chip due to software bottlenecks. To tackle one aspect of this problem, the authors propose a distributed algorithm that can load-balance packet processing workloads on a modem many-core architecture. The algorithm exploits parallelism and achieves load balancing by distributing processing task across different local regions of the chi. Workload distribution at chip level can be achieved with an O(n log n) time complexity and thus can scale to large configurations.
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