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Modern embedded compute platforms increasingly contain both microprocessors and Field-Programmable Gate Arrays (FPGAs). The FPGAs may implement accelerators or other circuits to speedup performance. Many such circuits have been previously designed for acceleration via Application-Specific Integrated Circuits (ASICs). Redesigning an ASIC circuit for FPGA implementation involves several challenges. The authors describe a case study that highlights a common challenge related to memories. The paper involves converting a pattern counting circuit architecture, based on a pipelined binary tree and originally designed for ASIC implementation, into a circuit suitable for FPGAs. The original ASIC-oriented circuit, when mapped to a Spartan 3e FPGA, could process 10 million patterns per second and handle up to 4,096 patterns.
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