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This paper describes a new fault-tolerant architecture to realize an Ethernet layer-2 switch. This architecture includes a memory buffer scheduler to assign memory buffers dynamically to the input ports of the switch. To evaluate this architecture and produce throughput and latency projections, the paper has developed a switch simulator called NUSIM. This simulation environment has helped them identify performance bottlenecks and consider tradeoffs of various switch design parameters. Their results show that dynamic input buffer assignment can decrease the number of dropped packets by approximately 30% on average, while also providing for increased reliability.
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