Dynamic Memory Scheduling Using FPGA
The new portable embedded applications such as media processors, where computation complexity is astronomical. Data transfers & huge number of memory accesses creates borderline for computational speed of signal processing. Memory access scheduling is important for media processor to use memory bandwidth more effectively. The paper targets to handle dynamic memory accesses while scheduling. Multitude of scheduling algorithms for memory controller targets read/write priority, this paper concerns refresh priority as well. The scheduler benefits the current memory controllers by increasing bus utilization rate while reducing execution time.