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Since power consumption has become a major constraint for the further throughput improvement of Chip MultiProcessors (CMPs), a key challenge is to optimize the performance of a CMP within a power budget limited by the CMP's cooling, packaging, and power supply capacities. Most existing solutions rely solely on Dynamic Voltage and Frequency Scaling (DVFS) to adapt the power consumption of CPU cores, without coordinating with on-chip L2 caches. However, dynamic cache resizing can be adopted to put rarely accessed cache ways into low-power modes, allowing power to be shifted to the CPU cores for improved performance.
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