Date Added: Aug 2009
A novel configurable processor architecture is presented for detecting Spatially Multiplexed (SM) data in a high order (4x4) Multiple-Input-Multiple-Output (MIMO) wireless systems. It is a customized architecture to match an algorithm that provides "Soft" values to the Forward Error Decoder (FEC), with systolic-like data and control flow. The processor is able to switch between three different modulation schemes (QPSK, 16-QAM, and 64-QAM) without any configuration latency. Preliminary synthesis results indicate that each detector core uses only about 18 Kilo Gate Equivalent (KGE) in addition to around 1800 storage flip-flops.