Hardware

Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design

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Executive Summary

The recent development of Non-Volatile Memory (NVM), such as Spin-Torque Transfer magnetoresistive RAM (STT-RAM) and Phase-change RAM (PRAM), with the advantage of low leakage and high density, provides an energy-efficient alternative to traditional SRAM in cache systems. The authors propose a novel Reconfigurable Hybrid Cache architecture (RHC), in which NVM is incorporated in the last-level cache together with SRAM. RHC can be reconfigured by powering on/off SRAM/NVM arrays in a way-based manner. In this paper, the authors discuss both the architecture and circuit design issues for RHC. Furthermore, they provide hardware-based mechanisms to dynamically reconfigure RHC on-the-fly based on the cache demand.

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