Hardware

Effect of Thread Level Parallelism on the Performance of Optimum Architecture for Embedded Applications

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Executive Summary

According to the increasing complexity of network application and internet traffic, network processor as a subset of embedded processors have to process more computation intensive tasks. By scaling down the feature size and emersion of Chip MultiProcessors (CMP) that are usually multithread processors, the performance requirements are somehow guaranteed. As multithread processors are the heir of uni-thread processors and there isn't any general design flow to design a multithread embedded processor, in this paper, the authors perform a comprehensive design space exploration for an optimum uni-thread embedded processor based on the limited area and power budgets.

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