Efficient and High-Performance Parallel Hardware Architectures for the AES-GCM Encryption and Decryption
The Advanced Encryption Standard (AES) is a symmetric key algorithm and its recently standardized authentication Galois/Counter Mode (GCM) have been utilized in various security-constrained applications. Many of the AES-GCM applications are power and resources constrained and require efficient hardware implementations. In this paper, different Application-Specific Integrated Circuit (ASIC) architectures of building blocks of the AES-GCM algorithms are evaluated and optimized to identify the high-performance and low-power architectures for the AESGCM. The implementation of GHASH operation requires 11-clock cycles for 128-block, and is pipelined with AES 12/14/16 clock cycles for 128/192/256-bits.