Efficient Congestion-Oriented Custom Network-on-Chip Topology Synthesis
The authors propose a new custom Network-on-Chip (NoC) topology synthesis methodology consisting of floorplanning, routers assignment, and routing paths calculation steps. The proposed heuristic methodology integrates fast algorithms based on the B-tree representation for floorplanning, on bipartite matching for the routers assignment step, and on multicommodity flow for congestion minimization for the routing paths calculation step. Hence, it is able to explore a large portion of the solution space efficiently. Network performance is estimated using an integrated cycle-accurate simulator. Experimental results demonstrate that custom irregular NoC topologies can achieve latencies comparable to those achieved by 2-layer 3D regular mesh topologies. The multicommodity flow based routing paths calculation is proven to be effective in improving the average latency at high packet injection rates.