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Efficient Implementation of a Pseudorandom Sequence Generator for High-Speed Data Communications

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Executive Summary

A conventional pseudorandom sequence generator creates only 1 bit of data per clock cycle. Therefore, it may cause a delay in data communications. In this paper, the authors propose an efficient implementation method for a pseudorandom sequence generator with parallel outputs. By virtue of the simple matrix multiplications, they derive a well-organized recursive formula and realize a pseudorandom sequence generator with multiple outputs. Experimental results show that, although the total area of the proposed scheme is 3% to 13% larger than that of the existing scheme, their parallel architecture improves the throughput by 2, 4, and 6 times compared with the existing scheme based on a single output.

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