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In this paper, an area-efficient symbol detector is proposed for Multiple-Input Multiple-Output (MIMO) communication systems with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing mode and spatial diversity mode in a single hardware, and shows the optimal Maximum Likelihood (ML) performance. By applying the multi-stage pipeline structure and using the complex multiplier based on polar-coordinate, the complexity of the proposed architecture is dramatically decreased. The proposed symbol detector was designed in Hardware Description Language (HDL) and synthesized to gate-level circuits using 0.13um CMOS standard cell library. With the proposed architecture, the total logic gate count for the detector is 393K, which is reduced by 57% compared with the conventional architecture.
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