Embedded Design of an Efficient Noise Canceller for Digital Receivers
This paper presents an error free and area efficient noise canceller for communication receivers. The proposed model has been designed and simulated using Microblaze microcontroller for efficient noise cancellation. The LMS algorithm has been used to design the noise canceller filter. LMS filter along with EDK Processor is presented. The proposed model has been designed and simulated using Simulink and System Generator blocks, synthesized with Xilinx Synthesis Tool (XST) and implemented on Virtex4 based xc4vsx35-10ff668 and Spartan 3E based xc3s500e-4fg320 FPGA device. The results show that the output of the EDK processor consisting of Microblaze microcontroller gives error free output.