Hardware

Energy-Aware Partitioned Fixed-Priority Scheduling for Chip Multi-Processors

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Executive Summary

Energy management is becoming an increasingly important problem in application domains ranging from embedded devices to data centers. In many such systems, multi-core processors are projected as a promising technology to achieve improved performance with a lower power envelope. Managing the application power consumption under timing constraints poses significant challenges in these emerging platforms. In this paper, the authors study the energy-efficient scheduling of periodic real-time tasks with implicit deadlines on Chip Multi-core Processors (CMPs). They specifically consider processors with a single voltage and clock frequency domain, such as the state-of-the-art embedded multi-core NVIDIA Tegra 2 processor and enterprise-class processors such as Intel's Itanium 2, i5, i7 and IBM's Power 6 and Power 7 series.

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