Date Added: Sep 2012
This paper presents the authors' experience in implementing the Advanced Encryption Standard (AES) algorithm. They have used 128 bit block size and 128 bit cipher key for the implementation. The AES also known as Rijndael algorithm is used to ensure security of transmission channels. Xilinx design tool 13.3 and Xilinx project navigator design tool are used for synthesis and simulation. Very high speed integrated circuit Hardware Description Language (VHDL) is used for coding. The fully pipelined design was implemented on Virtex 6 FPGA family and a throughput of 49.3Gbits/s was achieved with an operational frequency of 384.793 MHz.