Enhancing NBTI Recovery in 7T SRAM Cell through Fine-Grained Recovery Boosting
In each technology generation, CMOS digital circuits have advanced in three key aspects: speed, power, and reliability. However, with aggressive scaling in transistor dimension, temporal reliability degradation in MOSFET device is considered to be major problems. Negative Bias Temperature Instability (NBTI) is becoming a major reliability problem in the semiconductor industry. NBTI Aging of a Static Random Access Memory (SRAM) cell leads to a lower noise margin, thereby increasing the failure rate. When a negative voltage is applied at a p-channel transistor gate, interface traps are formed near oxide layer, causing a change in transistor characteristics.