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Systems designed with FPGAs benefit from significant improvements over ASICS, such as rapid-process technology scaling and design innovation, which permit the use of FPGAs in high-availability, high-reliability, and safety-critical systems. However, along with technology scaling come other effects such as increased susceptibility to soft errors that previously could be ignored. These soft errors, caused by Single Event Upsets (SEUs), are nondestructive and can be corrected without system downtime. This white paper explains how the SEU mitigation enhancements developed for Altera Stratix V FPGAs provide a strong roadmap to address soft-error system challenges.
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