Experiments for Accelerating IEEE 802.11i on Cyclone II FPGA
This paper presents hardware solutions for accelerating IEEE 802.11i. Several experiments were applied on the low-cost Cyclone II FPGA by using various architectures with different number of threads. The FPGA offloads the process of AES encryption from the master CPU. In addition, it offers the possibility of using several threads to run the AES encryption. Different optimizations have been applied on the hardware architecture of AES and on the basic unit of AES, in order to satisfy different constraints in terms of latency, area occupation and speed.