Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics

FPGA design of side-channel analysis countermeasures using unmasked dual-rail with pre-charge logic appears to be a great challenge. Indeed, the robustness of such a solution relies on careful differential placement and routing whereas both FPGA layout and FPGA EDA tools are not developed for such purposes. However, assessing the security level which can be achieved with them is an important issue, as it is directly related to the suitability to use commercial FPGA instead of proprietary custom FPGA for this kind of protection.

Provided by: Hindawi Publishing Topic: Hardware Date Added: Oct 2010 Format: PDF

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