Date Added: Oct 2009
Circuit-level timing speculation has been proposed as a technique to reduce dependence on design margins, eliminating power and performance overheads. Recent work has proposed micro-architectural methods to dynamically detect and recover from timing errors in processor logic. This paper has not evaluated or exploited the disparity of error rates at the level of static instructions. In this paper, the authors demonstrate pronounced locality in error rates at the level of static instructions. They propose timing error prediction to dynamically anticipate timing errors at the instruction-level and reduce the costly recovery penalty. This allows them to achieve 43.6% power savings when compared to a baseline policy and incurs only 6.9% performance penalty.