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By adjusting the design of the ISA and enabling circuit timing-sensitive optimizations in a compiler, the authors can more effectively exploit timing speculation. While there has been growing interest in systems that leverage circuit-level timing speculation to improve the performance and power-efficiency of processors, most of the innovation has been at the microarchitectural level. The authors make the observation that some code sequences place greater demand on circuit timing deadlines than others. Furthermore, by selectively replacing these codes with instruction sequences which are semantically equivalent but reduce activity on timing critical circuit paths, they can trigger fewer timing errors and hence reduce recovery costs.
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