Exploring the Feasibility of Low Cost Fault Injection Attacks on Sub-Threshold Devices Through an Example of a 65nm AES Implementation
The continuous scaling of VLSI technology and the aggressive use of low power strategies (such as sub-threshold voltage) make it possible to implement standard cryptographic primitives within the very limited circuit and power budget of RFID devices. On the other hand, such cryptographic implementations raise concerns regarding their vulnerability to both active and passive side channel attacks. In particular, when focusing on RFID targeted designs, it is important to evaluate their resistance to low cost physical attacks. A common low cost fault injection attack is the one which is induced by insufficient supply voltage of the chip with the goal of causing setup time violations. This kind of fault attack relies on the possibility of gracefully degrading the performance of the chip.