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High-speed serial protocols with increased data rates and expanded capabilities are addressing the demand for more network bandwidth. Efficiently supporting the subsequent increase in system bandwidth by attaining higher data rates and achieving greater integration is becoming an ever-greater challenge. This challenge includes targeting lower Bit Error Ratios (BERs) and ensuring signal and power integrity while maintaining power efficiency and optimizing design productivity. This white paper is an architectural exploration of SERDES challenges and solutions for 12.5-Gbps backplanes and next-generation optical modules at 28 Gbps. It describes the direction of the 10- to 28-Gbps transceiver industry, highlights the challenges, and introduces 28-nm silicon and productivity solutions that address these challenges.
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