F.P.G.A Implementation of Way Tagged Cache Into Chip Multiprocessors

Energy consumption has become a critical issue in many high performance microprocessors. Chip multiprocessors, CMP is only way to build high performance microprocessors. Most of the power dissipated in microprocessor is contributed by on-chip cache memories. This paper includes a CMP architecture in which way tagging is applied to cache memories for reducing energy consumption. Two core processors architecture with a shared L3 cache has been selected. For each core, the way information of L2 cache is maintained in the L1 cache and that of L3 cache in L2 cache.

Provided by: Creative Commons Topic: Hardware Date Added: Nov 2014 Format: PDF

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