Hardware

Fast and Compact ASIC Implementation of SFlash New Signature Scheme

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Executive Summary

The idea of using multivariate polynomials as public keys has attracted several cryptographers, SFlash signature scheme is a variant of the Matsumoto and Imai multivariate public Key cryptosystem and selected by NESSIE Consortium. In this paper the authors describe a hardware implementation of SFlash based on bit-parallel architectures to achieve high speed circuits for operations on Finite Fields which can be efficiently used as an authentication unit in wireless devices, smart cards and RFID networks. They have proposed a new generalization to Karatsuba-Ofman multiplier as the core of the design. An ASIC chip can be realized with 78K gates counts and 2.8 mm2 die size with 0.35 mm CMOS technology, with a maximum clock frequency 140 MHZ, which takes about 21.5ms to sign 259-Bits data.

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