Fast and Flexible High-Level Synthesis from OpenCL using Reconfiguration Contexts

High-level synthesis from OpenCL has shown significant potential, but current approaches conflict with mainstream OpenCL design methodologies due to orders-of-magnitude longer FPGA compilation times, and limited support for changing or adding kernels after system compilation. In this paper, the authors introduce a backend synthesis approach for potentially any OpenCL tool, which uses virtual coarse-grained reconfiguration contexts to speedup compilation by 4211x at a cost of 1.8x system resource overhead, while also enabling 144x faster reconfiguration to support different kernels and rapid changes to kernels.

Provided by: University of Florence Topic: Hardware Date Added: Oct 2013 Format: PDF

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