Networking

Fault Detection and Diagnosis in SRAM Based FPGA Using BIST

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Executive Summary

This paper presents a Built-In Self-Test (BIST) design for fault detection and fault diagnosis of Static-RAM (SRAM)-based Field-Programmable Gate Arrays (FPGAs). The proposed FPGA BIST structure can test both the interconnect resources [wire channels and Programmable Switches (PSs)] and LookUp Tables (LUTs) in the Configurable Logic Blocks (CLBs). The test pattern generator and output response analyzer are configured by existing CLBs in FPGAs; thus, no extra area overhead is needed for the proposed BIST structure. The target fault detection/diagnosis of the proposed BIST structure are open/short and delay faults in the wire channels, stuck on/off faults in PSs, and stuck-at-0/1 faults.

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