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High performance computing systems can be designed using parallel processing. The effectiveness of these parallel systems rests primarily on the communication network linking processors and memory modules. Hence, an interconnection network that provides the desired connectivity and performance at minimum cost is required. The design of a suitable interconnection network for inter-processor communication is one of the key issues of the system performance. In this paper a new multistage interconnection network IASEN (Irregular Augmented Shuffle Exchange) has been proposed modifying existing ASEN-2 network. ASEN-2 is a regular multipath network with limited fault tolerance.
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