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This paper proposes a new X-tolerant response compaction scheme with a practical assumption where the unknown values are generated on fixed scan chains. The proposed scheme guarantees fault diagnosis and treats simultaneous unknown logic values. In addition, it requires simple compactor structure composed of XOR gates, and it does not need any additional signal from the outside. All products should pass proper test processes for going to markets. A chip, one of core products in semiconductor industries, is also one of products, and the authors cannot call a chip as a completely made product without testing. Therefore, the test cost is an important factor driving time-to-market and cost of production.
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