Flexible Cache Error Protection Using an ECC FIFO

Date Added: Nov 2009
Format: PDF

The authors present ECC FIFO, a mechanism enabling two-tiered last-level cache error protection using an arbitrarily strong tier-2 code without increasing on-chip storage. Instead of adding redundant ECC information to each cache line, their ECC FIFO mechanism off-loads the extra information to off-chip DRAM. They augment each cache line with a tier-1 code, which provides error detection consuming limited resources. The redundancy required for strong protection is provided by a tier-2 code placed in off-chip memory. Because errors that require tier-2 correction are rare, the overhead of accessing DRAM is unimportant.