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The pertinent choice of flip-flop topologies is an essential importance in the design of VLSI integrated circuits for high speed and high performance CMOS circuits. Understanding the suitability of flip-flops and selecting the best topology for a given application is an important issue to fulfill the need of the design to satisfy low power and high performance circuit. This paper presents a widespread comparison of existing flip-flop classes and topologies in terms of its area, transistor count, parasitic values and power dissipation. In particular the comparison strategy includes the elucidation of circuit operation, simulation setup, parasitic estimation, area estimation, power dissipation estimation. An overview of the optimum design strategy is also presented.
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