Hardware

Floorplacement for Partial Reconfigurable FPGA-Based Systems

Date Added: Dec 2010
Format: PDF

The authors presented a resource- and configuration-aware floor-placement framework, tailored for Xilinx Virtex 4 and 5 FPGAs, using an objective function based on external wirelength. Their work aims at identifying groups of Reconfigurable Functional Units that are likely to be configured in the same chip area, identifying these areas based on resource requirements, device capabilities, and wirelength. Task graphs with few externally connected RRs lead to the biggest decrease, while external wirelength in task graphs with many externally connected RRs show lower improvement.