Hardware

Folded Architecture of Scheduler for Area Optimization in On-Chip Switch Fabric

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Executive Summary

As the feature sizes of the manufacturing processes are constantly shrinking, the possibility and demand for more functionality on a single chip goes up. This can lead to many problems e.g. as the memory access bandwidth through the bus gets too low to cope with the demand, also the electrical performance of the bus gets degraded as the number of modules are increased. The authors' proposed architecture makes use of a switch fabric structure to eliminate the traditional drawbacks of bus based design. Scheduler becomes the integral part of the switch which decides the scheduling of the SOC devices. In this paper, they have proposed an area efficient scheduler which saves around 22 - 26% of the total scheduler area on the silicon die.

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