Date Added: Oct 2009
In the field of process control, data acquisition modules (such as device drivers) require special care in their design, because they usually stand as bottlenecks between hardware devices and control applications. In particular timing constraints on occurrences of data are often given based on intuition and empirical experience. The paper presented here intends to provide a formal model to characterize timing properties such as input data delay. As an illustration, a model of a simple data acquisition module is presented. The authors show how the formal model can be exploited to establish bounds of delay.