FPGA Based an Advanced Lut Methodology for Design of a Digital Filter
The present manuscript proposes an advanced methodology based on which the LUT is modeled through which an FIR filter is designed for efficient area utilization. As it is a known fact that most of the DSP processors concerned with the multiply and accumulate structures rather than the memory mapping structures, this paper presents the methods to reduce the need of the additional components needed with in the DSP cores used in FPGA. So far, several methods have been proposed to optimize the memory size. Here a new approach is specified that further eliminate the drawbacks due to the use of multiply and accumulate structures.